1. Field of the Invention
The present invention relates to a power semiconductor device and a method for producing the same.
2. Description of the Related Art
U.S. Pat. No. 4,783,690 discloses a power semiconductor element having integrated vertical type double diffused insulated-gate transistors (DMOS transistors). To fabricate the integrated DMOS transistors, this disclosure prepares a high concentration substrate of a first conductivity type, forms a low concentration layer of the first conductivity type over the substrate, and forms a deep well (a main well) of a second conductivity type as well as a channel well of the second conductivity type in the layer. The main well does not extend under a gate electrode. The channel well is shallower than the main well and reaches a channel under the gate electrode to determine the threshold voltage of the transistor. The disclosure then forms a high concentration source of the first conductivity type in the channel well.
There has been proposed a power semiconductor device (an intelligent power element) employing such DMOS transistors as well as NMOS transistors. A subwell of the second conductivity type is formed in a layer on which the DMOS transistor is formed, and a planar (lateral) NMOS transistor is formed in the subwell. The NMOS transistor serves as a control element for the DMOS transistor.
The subwell may be simply formed in the same process for forming a main well for the DMOS transistor. When the main well and subwell are formed in the same ion implantation process, they may have the same depth and the same concentration distribution. This provides the following problem.
To drive the intelligent power element with a low voltage supply, it is necessary to lower the threshold voltage Vt of the DMOS transistor. The low threshold voltage may be realized by a low impurity concentration in the channel well of the DMOS transistor. This increases the reach-through withstand voltage of the DMOS transistor, and narrows the difference between the reach-through withstand voltage of the DMOS transistor and that of the NMOS transistor. As a result, when the DMOS transistor causes a reach-through phenomenon, the same phenomenon also occurs at the NMOS transistor, so that the NMOS transistor, having a smaller allowable current, will break down earlier than the DMOS transistor.
This problem usually occurs when intermittently controlling a reactive load. This will be explained more precisely.
In the intelligent power element, a substrate, i.e., a drain is connected to a high-potential power source (for example, a positive power source) through the reactive load. When a gate is turned OFF, the reactive load applies a back electromotive voltage to the substrate. When the back electromotive voltage exceeds the reach-through withstand voltage of the DMOS or NMOS transistor, a reach-through phenomenon occurs.
FIG. 20(a) shows results of reactive load tests carried out with a test circuit of FIG. 20(b) on semiconductor devices having threshold voltages Vt of 3 V and 1.8 V. These different threshold voltages of the devices are materialized by controlling the impurity concentration in the channel wells of the devices.
In FIG. 20(a), the abscissa represents the inductance of the reactive load and the ordinate represents breakdown current. When L=1 mH, the device of Vt=3 V has an allowable current of 20 A, while the device of Vt=1.8 V has an allowable current of only about 4 A. When L=5 mH or over, the device of Vt=1.8 V substantially shows no allowable current.
These test results will be analyzed.
The reason why the allowable current of the device of Vt=1.8 V is low will be analyzed at first. Only the source of each lateral NMOS transistor was damaged in the tests. (Usually, the source of an NMOS transistor has a lower potential and a higher reach-through electric field than the drain thereof.) On the other hand, the device of Vt=3 V having a higher reach-through withstand voltage was damaged at its DMOS transistors.
Decreasing the threshold voltage Vt of the DMOS transistor from 3 V to 1.8 V is materialized by decreasing the impurity concentration of the channel well of the DMOS transistor. When the channel well is low in impurity concentration, a junction depletion layer in the main well of the DMOS transistor extends upwardly. This results in increasing the reach-through withstand voltage of the DMOS transistor.
In the device of Vt=1.8 V, the reach-through withstand voltage of the DMOS transistor is nearly equal to that of the NMOS transistor. Accordingly, when a breakdown occurs in the DMOS transistor, the same will always occur in the NMOS transistor. Namely, the source of the NMOS transistor, having a small allowable current, breaks down and reduces the allowable (withstand) current of the device.
On the other hand, in the device of Vt=3 V, the reach-through withstand voltage of the DMOS transistor is sufficiently lower than that of the NMOS transistor, so that the DMOS transistor, having a larger allowable current, first suffers a reach-through breakdown to absorb current due to the accumulated energy of the reactive load. Namely, the DMOS transistor having a large allowable (withstand) current provides the device with a large breakdown current.
Results of tests carried out on samples of Vt=3.2 V and Vt=1.8 V will be explained. These samples had an n.sup.+ substrate of 10.sup.20 atoms/cc or over, an n.sup.- epitaxial layer of 5.times.10.sup.15 atoms/cc formed on the substrate, and a p.sup.- main well and a subwell of 3.times.10.sup.13 dose/cm.sup.2 each. A p.sup.- channel well of the sample of Vt=3.2 V was of 1.times.10.sup.14 dose/cm.sup.2, and that of the sample of Vt=1.8 V was of 7.times.10.sup.13 dose/cm.sup.2.
In the sample of Vt=3.2 V, each DMOS transistor had a reach-through withstand voltage of 85 V and each NMOS transistor had a reach-through withstand voltage of 90 V, and had an allowable current of 16 to 18 A with respect to a reactive load of 5 mH. On the other hand, in the sample of Vt=1.8 V, each DMOS transistor had a 90 V withstand voltage and each NMOS transistor had a 91 V withstand voltage. Since the withstand voltages of the DMOS and NMOS transistors of the sample of Vt=1.8 V are nearly equal to each other, the NMOS breaks down successively and provides the sample with an allowable current of only 1 A or less.